 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| - Preliminary - E910.27A External Adjustable High Efficiency PFM Step-Down Converter Features * * * * * * * * * * * * * * Brief Functional Description The easy to use hysteretic step-down converter provides high efficiency over a wide load and input range with few external components. An advanced PFM control scheme gives this device the benefits of a PWM converter with high efficiency at heavy loads, while using very low operating current at light loads to maintain an excellent behaviour over load variation. Maximum switching frequency of 300kHz permits small external components and operation to 100% duty cycle allows the lowest possible dropout voltage. For optimal flexibility an external shunt resistor sets the maximum output current. The converter contains a selectable internal reference with high or low voltage to regulate a wide range of output voltage or output current. The reference for output regulation can also be provided from an external source, like DAC. A selectable power good, reset or watchdog signal is provided. An external capacitor sets the reset output pulse duration and / or watchdog trigger time. An optional internal short delay timeout can greatly reduce the losses of the whole application in case of short or overload. Very low shutdown and quiescent currents and the wide input voltage range makes the converter ideal for battery powered systems. More than 90% efficiency and 100% duty cycle Wide input voltage range from 5V to 40V Integrated 1.6A on-chip P-channel MOS power switch 12A typical shutdown current Less than 0.5V drop voltage at 500mA output current 0.2V to Vinput adjustable output range Controllable VOUT via an external Reference No control loop compensation required Improved current-limited PFM converter Maximum operating frequency > 300kHz Power good, reset or watchdog signal Under-voltage lockout and thermal shutdown -40C to 125C junction temperature Available in thermally enhanced TSSOP24 package Applications * * * * * Automotive electronics Minimum component step-down converter Sequenceable POL power supply systems Externally controllable LED power supply Externally controllable power amplifier Typical Application VINPUT VS CDR RS CIN ENPS SMON, RSEL VSM CDRV RSIN E91027 RLEV, WEN, WDI,SLDY GND, SGND, AGND VOUTPUT SWD CSM PGND RFEX LCK COUT VFB DSW DAC RFB1 RFB2 ELMOS Semiconductor AG Specification 1 / 50 03SP0357E.00 05.09.2006 - Preliminary 1 General 1.1 WARNING - Life Support Applications Policy E910.27A ELMOS Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing ELMOS Semiconductor AG products, to observe standards of safety, and to avoid situations in which malfunction or failure of a ELMOS Semiconductor AG Product could cause loss of human life, body injury or damage to property. In development your designs, please ensure that ELMOS Semiconductor AG products are used within specified operating ranges as set forth in the most recent products specifications. 1.2 General Disclaimer Information furnished by ELMOS Semiconductor AG is believed to be accurate and reliable. However, no responsibility is assumed by ELMOS Semiconductor AG for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of ELMOS Semiconductor AG. ELMOS Semiconductor AG reserves the right to make corrections, modifications, enhancements, improvements, and other changes to the products contained in this datasheet at any time to improve performance, reliability, or manufacturability without notice. 1.3 Application Disclaimer Circuit diagrams external to ELMOS Semiconductor AG products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Customers are responsible for their products and applications using ELMOS Semiconductor AG components. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of ELMOS Semiconductor AG or others. Information published by ELMOS Semiconductor AG regarding third-party products or services does not constitute a license from ELMOS Semiconductor AG to use such products or services or a warranty or endorsement thereof. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. 1.4 Contact ELMOS Semiconductor AG Heinrich-Hertz-Strae 1 D-44227 Dortmund Germany Phone: +49 (0) 231 7549 0 Fax.: E-mail: Web: +49 (0) 231 7549 149 info@elmos.de www.elmos.de Copyright @ 2006 ELMOS Semiconductor AG Reproduction, in part or whole, without the prior written consent of ELMOS Semiconductor AG, is prohibited. ELMOS Semiconductor AG Specification 2 / 50 03SP0357E.00 05.09.2006 - Preliminary 2 Pinout 2.1 Pin Description Name RSIN1 E910.27A Pin No. 1 Typ A, I, HV Description PFM current sense comparator input and source terminal of internal P-MOSFET. Connect currentsense resistor between VS and RSIN. Internal power P-MOSFET is turned off when the voltage across this resistor is equal to or greater than the current limit trip level. External filter for extensive high frequency noise may be necessary. PFM current sense comparator input and source terminal of internal P-MOSFET. Connect currentsense resistor between VS and RSIN. Internal power P-MOSFET is turned off when the voltage across this resistor is equal to or greater than the current limit trip level. External filter for extensive high frequency noise may be necessary. High side linear regulator output. CDRV provides a regulated output voltage that is VDRV below VS. The internal power P-MOSFET gate is driven between VS and CDRV. Bypass CDRV to VS with a high quality ceramic capacitor. There must be always a capacitor connected between VS and CDRV. In rare circuit configurations an external schottky diode must be connected between this pad and PGND to avoid malfunction through exessive substrat currents. Positive power stage supply input. Also acts as a voltage sense point for the internal current sense comparator. Bypass VSP to PGND with a ceramic capacitor in parallel with a low-ESR electrolytic capacitor. Positive analog power supply input. Bypass VSA to AGND with a ceramic capacitor. Shutdown input. Connect ENPS to VS for normal operation. Drive ENPS to false to shut the part in shutdown. In shutdown mode most internal circuits are turned off. The thresholds are CMOS level compatible and a small pull-down current is drawn. Active-high SMON control input. When SMON is false the internal linear regulator is already working and can supply current to an external load. But the rest of the internal circuits are turned off. Thermal shutdown is already working. The thresholds are CMOS level compatible and a small pull-down current is drawn. Use this input for sequencing. Internal linear regulator output. VSM provides power to the internal circuity and can supply a specified amount of current to an external load. Bypass VSM to AGND with a high quality ceramic and parallel low-ESR tantal or equivalent, capacitors. All electrical specifications are valid until VSM is settled only. Signal ground. SGND requires a short low noise connection to ensure good load regulation. The internal reference is referred to this ground, so errors at this pin are multiplied by the error comparator. Analog ground. AGND requires a short low noise connection to ensure good VSM regulation. The low drop preregulator powers most of internal circuits. Feedback input is the error comparator inverting input, and controls output voltage by adjusting switch duty cycle. VFB also aids power good detection circuit. Connect a resistor divider between VOUTPUT, VFB and SGND for the desired output voltage. In case of outer loop current regulation connect VFB to an external sense resistor. If enabled, external reference input is the error comparator noninverting input reference and controls the voltage VOUTPUT. In this case power good, reset and watchdog functions are disabled. Open drain logic true output for indicating an internal fault. Errors are VSM under voltage lockout, driver voltage low and ASIC over temperature. When true, the PFM inserts an additional delay after an overcurrent pulse. The switching frequency decreases due to the larger duty cycle. This function reduces greatly the power consumption in case of a fault. The thresholds are CMOS level compatible. When false selects internal high-reference voltage and when true internal low-reference voltage. The thresholds are CMOS level compatible. When false selects internal reference generator and when true external reference voltage input at port RFEX. The thresholds are CMOS level compatible. Watchdog trigger input. The rising edge of an input pulse resets the watchdog. This function is with internal references available only. The thresholds are CMOS level compatible. RSIN2 2 A, I, HV CDRV 3 A, O, HV VSP VSA ENPS 4 5 6 S, HV S, HV D, I, HV SMON 7 D, I, HV VSM SGND AGND 8 9 10 A, O S S VFB 11 A, I RFEX ERR SDLY RLEV RSEL WDI 12 13 14 15 16 17 A, I D, O D, I D, I D, I D, I ELMOS Semiconductor AG Specification 3 / 50 03SP0357E.00 05.09.2006 - Preliminary Name WEN PWGD CDLY GND PGND SWD1 SWD2 E910.27A Pin No. 18 19 20 21 22 23 24 Typ D, I D, O A, I S S A, O, HV A, O, HV Description Watchdog enable input. When true watchdog function is enabled. This function is with internal references available only.The thresholds are CMOS level compatible. The PWGD open drain output stays low for undervoltage condition at VFB and in case of internal error. Use this output for sequencing or in combination with an external timing capacitor at CDLY for reset delay timer function and watchdog timeout. This function is with internal references available only. Delay timing capacitor input. Connect a timing capacitor between CDLY and GND to set the reset output duration and watchdog trigger time. ESD structure and substrat ground return for internal circuits. Make a short connection between this port and the other grounds. A low impedance circuit ground plane is highly recommended. High current power ground return for internal circuits. Make a short connection between this port, the free-wheel diode, input and output capacitors. Due tue high frequency currents, a low impedance circuit ground plane is highly recommended. Drain output of the internal power P-MOSFET. Connect the external choke and the free-wheel diode to this port. Drain output of the internal power P-MOSFET. Connect the external choke and the free-wheel diode to this port. D = Digital, A = Analog, S = Supply, I = Input, O = Output, HV = High Voltage (max. 40V) ELMOS Semiconductor AG Specification 4 / 50 03SP0357E.00 05.09.2006 - Preliminary 2.2 Package Pinout E910.27A Top View RSIN1 RSIN2 CDRV VSP VSA ENPS SMON VSM SGND AGND VFB RFEX 1 2 3 4 5 24 23 22 21 20 SWD2 SWD1 PGND GND CDEL PWGD WEN WDI RSEL RLEV SDLY ERR 6 7 8 9 10 11 12 Exposed Pad (Bottom) 19 18 17 16 15 14 13 Exposed Pad must be connected to GND Figure 2.2-1: Pinout TSSOP24 ADT-1 ELMOS Semiconductor AG Specification 5 / 50 03SP0357E.00 05.09.2006 - Preliminary 3 Basic Blockdiagram E910.27A VSA ENPS SMON VSM CCMP RFEX RSEL RLEV VCMP PFM MUX VR1 VR2 REFERENCE POWER SUPPLY VSP E91027 CDRV VILIM RSIN1 RSIN2 AGND VREF HSDRV SWD1 PWGD OVTMP UVLO SGND CDLY WDI WEN VFB ERR SDLY GND PGND SWD2 PWRGOOD ERRPROC Figure 3-1: Blockdiagram ELMOS Semiconductor AG Specification 6 / 50 03SP0357E.00 05.09.2006 - Preliminary 4 Operating Conditions 4.1 Absolute Maximum Ratings E910.27A Stresses beyond those listet under absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated above is not implied. Expose to absolute maximum rated conditions for extended periods may effect device reliability and are not permitted. AGND, SGND, PGND and Exposed Pad must be soldered to GND and stand for future reference within text as GND. VSA and VSP must be always external interconnected and stand for future reference within text as VS. RSIN1 and RSIN2 must be always external interconnected and stand for future reference within text as RSIN. SWD1 and SWD2 must be always external interconnected and stand for future reference within text as SWD. Parameter Supply voltage input VS Supply voltage input VS (Load dump) VSM to GND IVSM CDRV to GND CDRV to VS RSIN to VS IRSIN SWD to GND ISWD ENPS to GND SMON to GND RLEV to GND RSEL to GND RFEX to GND SDLY to GND VFB to GND CDLY to GND PWGD to GND IPWGD WEN to GND WDI to GND ERR to GND IERR Maximum input current in protection circuitry on any pin ESD Protection Condition tw<400ms Symbol VS VSmax VSM IVSM VCDRVG VCDRV VRSIN IRSIN VSWD ISWD VENPS VSMON VRLEV VSEL VRFEX VTOEN VFB VCDLY VPWGD IPWGD VWEN VWDI VERR IERR IPROT Min. -0.3 -0.3 -0.3 0 -0.3 VS-7.0 VS-1.0 0 -2.0 0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0 -0.3 -0.3 -0.3 0 -10 -1.5 Max. 40 45 5.5 -20 VS VS VS+0.3 2 VS -2 40 40 VSM VSM VSM VSM VSM VSM 8 4 VSM VSM 8 4 10 1.5 Unit V V V mA V V V A V A V V V V V V V V V mA V V V mA mA kV HBM; R=1.5K, C=100pF VESD ELMOS Semiconductor AG Specification 7 / 50 03SP0357E.00 05.09.2006 - Preliminary Parameter Capacitor between VS and CDRV Continuous power dissipation Derate 7.5mW/C above +20C Continuous power dissipation 1) Derate 25mW/C above +105C Thermal resistance junction to ambient Thermal resistance junction to ambient Thermal resistance junction to case Operating temperature Junction temperature Storage temperature 1) Package mounted on FR4 50x50x1.5mm; 70 Cu, zero airflow 1) E910.27A Min. 150 -40 -40 -40 Condition ceramic (X7R) or better @ TA = +20C @ TA = +105C Symbol CDR PVTOT PVTOT RTJA Max. 1000 800 160 40 5 125 140 150 Unit nF mW mW K/W K/W K/W C C C PCB heat sink area 500mm RTJACLD RTJC TA TJ TSTG This integrated circuit can be damaged by ESD. ELMOS Semiconductor AG recommends that all integrated circuits must be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtile performance degradation to complete device failure. ELMOS Semiconductor AG Specification 8 / 50 03SP0357E.00 05.09.2006 - Preliminary 4.2 Recommended Operating Conditions E910.27A Parameters are guaranteed within the range of operating conditions unless otherwise specified. -40C < TJ < 125C Parameter Supply voltage Supply bypass capacitance Source impedance at VFB External reference voltage at RFEX Linear regulator bypass capacitance Driver regulator bypass capacitance ERR output current PWGD output current POR and WD timing capacitance DSW max. reverse recovery time Operating temperature Range Condition 100nF bypass, ceramic (X7R) ceramic (X7R) or better RFB1//RFB2 Zi < 2kOhm ceramic (X7R) or better ceramic (X7R) or better VERRL < 0.50V VPWGD < 0.50V ceramic (NPO / X7R) IF/ IR = 2A PVTOT within limits Symbol VS CIN RVFB VRFEX CSM CDR IERR IPWGD CDLY TRR TOP Min. 5 100 0 1 330 0.2 0.2 0 - 40 Max. 40 2 1.30 10 1000 2 2 1 30 105 Unit V nF kOhm V F nF mA mA F ns C All voltages are referred to GND, and currents are positive when flowing into the node unless otherwise specified. ELMOS Semiconductor AG Specification 9 / 50 03SP0357E.00 05.09.2006 - Preliminary 5 Detailed Electrical Characteristics E910.27A The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical values represent the mean values at room temperature, which are related to production processes. 5.1 Supply Voltage and Currents No. 1 2 3 4 5 Parameter Input voltage range Shutdown mode current into VS ENPS input high threshold ENPS linput low threshold ENPS input pull down current ENPS=false SMON=false VS=>6V 5V No. 1 2 3 4 5 6 7 8 9 1) Parameter Output voltage Dropout voltage External available output current Output short current Condition 6V 3) Min. 4.50 10 20 140 - Typ. 5 0.5 170 2.2 0.8 2 3 Max. 5.50 15 120 200 - Unit V V mA mA A V V A mA ENPS=true, Idle quiescent supply current SMON=false, VS=>6V, into VS (stand-by) IVSM=0A SMON input high threshold SMON input low threshold SMON input pull down current Device quiescent current 6V not switching 2) VS => 5V, VSM > 4V, ENPS = true, SMON = true, VS = 12V, ENPS = true, SMON = true; CDR = 220nF, VFB = VSM 5.3 Internal VSM Undervoltage Lockout Level No. 1 2 1) Parameter VSM level true VSM level false Condition 1) 1) Symbol VCLRL VCLRH Min. - Typ. 3.90 3.60 Max. - Unit V V SMON=true SMON=true Ensured by design. Not production tested. ELMOS Semiconductor AG Specification 10 / 50 03SP0357E.00 05.09.2006 - Preliminary 5.4 MUX No. 1 2 3 4 5 6 7 8 9 1) E910.27A Parameter RFEX input voltage range RFEX input current RFEX feedthrough loss RSEL level true RSEL level false RSEL input current RLEV level true RLEV level false RLEV input current Condition 1) 1) Symbol VRFEX IRFEX VLRFEX VRSELH VRSELL IRSEL VRLEVH VRLEVL IRLEV 2) Min. 0 - Typ. -1 10 0.65xVSM 0.26xVSM 1 0.65xVSM 0.26xVSM 1 Max. 1.30 -3 - Unit V A mV V V A V V A 0V < VRFEX < 1.3V 1) 2) Source Impedance < 2kOhm 1) 2) 1) 2) 1) 1) 2) 1) 2) 1) VS => 5V, VSM > 4V, ENPS = true, SMON = true, Ensured by design. Not production tested. 5.5 Voltage Comparator No. 1 2 3 4 5 6 1) Parameter Effective VFB offset voltage VFB input current VFB reference voltage H VFB reference voltage L Static VFB hysteresis Condition 1) 2) 1) 1) 1) 1) 2) Symbol VOFF IVFB VR1 VR2 VCMPHYST TRHFB Min. -10 1.165 194 Typ. 0 -1 1.200 200 4 Max. 10 -3 1.236 206 Unit mV A V mV mV VS=12V, VFB propagation time to SW VR1+/-100mV output Tj=25C, RSW=50Ohm 2) - 100 - ns VS => 5V, VSM > 4V, ENPS = true, SMON = true, Ensured by design. Not production tested. 5.6 Current Comparator No. 1 2 1) Parameter Threshold level Propagation time to SWD output Condition 1) Symbol VCLIM TRHCL Min. VS-170m - Typ. VS-200m 100 Max. VS-230m - Unit V ns VS=12V, Tj=25C, RS=1.30Ohm, RSW=50Ohm 2) 2) VS => 5V, VSM > 4V, ENPS = true, SMON = true, Ensured by design. Not production tested. ELMOS Semiconductor AG Specification 11 / 50 03SP0357E.00 05.09.2006 - Preliminary 5.7 Pulse Frequency Modulator No. 1 2 3 4 5 1) E910.27A Parameter Minimum SW off-time Minimum SW off-time Minimum SW on-time Blanking time Duty cycle Condition 1) 1) Symbol TOFFM TOFFMS TONM TBLK DCYC 2) Min. 1.5 14 0.5 0 Typ. 2 20 1 300 - Max. 2.5 26 1.5 100 Unit s s s ns % SDLY = false SDLY = true and CCMP activeted 1) 1) 2) 1) 2) VS => 5V, VSM > 4V, ENPS = true, SMON = true, Ensured by design. Not production tested. 5.8 Power Stage No. 1 2 3 4 5 6 1) Parameter ON resistance RSIN voltage range SWD voltage range Minimum sink current by internal regulator Driver lockout voltage Driver voltage Condition 1) 1) 1) Symbol RDSON VRSR VSWR Min. VS-1000m -2.0 5 4.5 Typ. 0.50 VS-200m 8 3.74 5.20 Max. 0.80 VS VS 6.5 Unit Ohm V V mA V V VS-CDRV = 5V 1) 2) CDR = 220nF CDR = 220nF IDRVS VDRVL VDRV 1) 2) 1) 2) between VS and CDRV, CDR = 220nF 2) VS => 5V, VSM > 4V, ENPS = true, SMON = true, static value 5.9 Error Output and Optional Short Detection Delay Input No. 1 2 3 4 5 1) Parameter SDLY level true SDLY level false ERR open drain voltage range ERR low voltage ERR leakage current Condition 1) 2) 1) 2) Symbol VSDLH VSDLL Min. 0 - Typ. 0.65xVSM 0.26xVSM 0.50 - Max. 6 0.80 10 Unit V V V V A 1) 2) ERR = false VERRH VERRL IERRL 1) 1) IERR<= 1mA VERR = 5V 2) VS => 5V, VSM > 4V, ENPS = true, SMON = true, Ensured by design. Not production tested. 5.10 Power Good / Reset and Watchdog Stage No. 1 2 3 4 5 Parameter PWGD threshold PWGD hysteresis PWGD low voltage PWGD open drain voltage range PWGD leakage current Condition 1) 1) Symbol VPWGDT VPWGDY VPWGDL VPWGDR IPWGDL Min. 0 - Typ. 0.90xVFB 0.05xVFB 0.50 - Max. 0.80 6 10 Unit V V V V A PWGD = false IPWGD <= 2mA 2) PWGD = true VPWGD = 5V ELMOS Semiconductor AG Specification 12 / 50 03SP0357E.00 05.09.2006 - Preliminary No. 6 Parameter Minimum required pulse duration at VFB for PWGD response Condition VFB=1.200V overdrive=-250mV int. VREF=1.2V CDLY = 100nF 1) 2) VFB=1.050V overdrive=+/-200mV int. VREF=1.2V CDLY = 0nF 1) 2) 1) 2) 1) 2) 1) 1) 2) E910.27A Typ. Max. Unit s Symbol TREC Min. 2 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1) PWGD delay without CDLY Upper reset timing threshold Reset saturation voltage Reset discharge resistance Reset charge current Reset delay with CDLY WEN level true WEN level false WDI level true WDI level false Watchdog trigger pulse duration Upper watchdog switching threshold Lower watchdog switching threshold Watchdog charge current Watchdog discharge current Watchdog period Watchdog trigger time TPWGD VRUD VRLD RRDC IRSTC TRST VWENH VWENL VWDIH VWDIL TWDI VWUD VWLD IWDC IWDD TWDP TWDTR 0.75xVSM 0 9 15 200 0.75xVSM 0.15xVSM 9 1.68 75 63 40 0.8xVSM 15 15 25 0.65xVSM 0.26xVSM 0.65xVSM 0.26xVSM 0.8xVSM 0.2xVSM 15 2.80 125 105 0.85xVSM 0.5 21 35 0.85xVSM 0.25xVSM 21 3.90 175 147 s V V Ohm A ms V V V V ns V V A A ms ms CDLY = 100nF CDLY = 100nF VSM = 5V VCDLY=2.5V VSM = 5V CDLY = 100nF 1% 1) 2) 1) 2) 1) 2) 1) 2) 1) 2) Reaction on trailing edge only 1) 2) 1) 2) CDLY = 100nF CDLY = 100nF 1) 2) 1) VSM = 5V VCDLY=2.5V VSM = 5V VCDLY=2.5V 1) 1) 2) VSM = 5V CDLY = 100nF 1% 1) 2) VSM = 5V CDLY = 100nF 1% VS => 5V, VSM > 4V, ENPS = true, SMON = true, 2) Ensured by design. Not production tested. 5.11 Thermal Shutdown No. 1 2 1) Parameter Shutdown temperature Hysteresis Condition 1) 1) Symbol KTMPS KTMPH Min. - Typ. 160 30 Max. - Unit C C VS > 5V VS > 5V Ensured by design. Not production tested. ELMOS Semiconductor AG Specification 13 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A 6 Typical Performance Characteristics Shutdown current vs. input volt. and temperature Reference voltages over temperature Idle current vs. input voltage and temperature Current sense trip level vs. temperature VSM Voltage over input voltage and temperature Swtich ON-resistance vs. temperature ELMOS Semiconductor AG Specification 14 / 50 03SP0357E.00 05.09.2006 - Preliminary Minimum switch on-time vs. temperature E910.27A PWGD delay vs. capacitance and temperature Minimum switch off-time vs. temperature WD period vs. capacitance and temperature Short case (SDLY=1) min. swtich off time vs. temp. ELMOS Semiconductor AG Specification 15 / 50 03SP0357E.00 05.09.2006 - Preliminary 7 Functional Description 7.1 Operation 7.1.1 Typical Application Circuit VINPUT E910.27A CIN VSA ENPS SMON VSM CSM RFEX RSEL RLEV VCMP PFM HSDRV VOUTPUT LCK MUX VR1 VR2 REFERENCE CCMP VILIM POWER SUPPLY VSP E91027 CDR CDRV RS RSIN1 RSIN2 AGND VREF SWD1 For Sequencing or RESET PWGD OVTMP UVLO SGND RPU CDLY WDI WEN VFB ERR SDLY GND PGND COUT CDLY From VSM or VOUTPUT RFB1 RFB2 SWD2 PWRGOOD ERRPROC DSW Figure 7.1.1-1: Typical Application Circuit 7.1.2 Introduction The E910.27 is a user friendly high voltage CMOS step-down DC-DC converter that provides an external controllable output voltage. It features an internal 500mOhm (typically) P-channel MOS transistor switch for high efficiency over a wide range of input/output voltages and currents. Moreover the converter can be operated over a very wide input supply range from 5V to 40V with typically 12A shutdown and typically 170A stand by current, making them optimal for use in applications as automotive and industrial control. Its sophisticated control scheme combines the advantages of pulse-skipping pulse-frequency modulation (low supply current) and pulse-width modulation (high efficiency with heavy loads), providing high efficiency over a wide input voltage and output current range. Operation up to 100% duty cycle allows the lowest possible dropout voltage, which allows a wider input voltage variation. Its small size, high switching frequency, and low external parts count minimise the required circuit board area and component cost. A reset signal is generated for a voltage at VFB below a level of VREF-15%. The watchdog circuit monitors a connected controller. If there is no positive going edge at the watchdog input WDI within a fixed time, the PWGD output is set low. The delay for power on reset and the maximum permitted watchdog pulse period can be set externally with capacitor CDLY. Figure 7.1.1-1 shows the E910.27 in a typical application circuit. ELMOS Semiconductor AG Specification 16 / 50 03SP0357E.00 05.09.2006 - Preliminary 7.2 Linear Regulators 7.2.1 Internal Power Supply E910.27A The internal high PSRR power supply allows the E910.27 to operate from typically 4.5V up to 40V input voltage (VSA), while drawing a constant very low quiescent current (ISHTD). This allows the use in automotive K30 systems. It is always on and supports the internal regulators, thermal protection circuits, undervoltage lockout circuits and error logic's with stable reference voltages and currents. 7.2.2 VSM Regulator The power supply block contains also a short and thermal protected low quiescent current 5V low drop linear regulator (VSM). It will be switched on via a high level at Pin ENPS. Output VSM can provide at minimum 10mA to an external load (e.g. stand by circuits). Due to the very wide input level range from 0V to VSMAX, and CMOS compatible thresholds the ENPS input can be driven by controllers, bus transceivers (e.g. CAN), K15D applications and used for power sequencing. In SMPS operating mode (SMON=true) the linear regulator powers the internal SMPS circuits. When the input voltage VSA goes below about 4V and therefore VSM drops down to the level VCLRH the E910.27 enters into undervoltage lockout state, the internal P-channel MOS transistor is switched off and the ERR output goes low. Bypass VSM with a good quality capacitor (CSM) to the small signal ground. 7.3 Device Quiscent Currents Mode Shutdown (Idle) VSM ON (linear regulator on, not externally loaded) SMPS ON (not switching) ENPS 0 1 1 SMON 0 0 1 Device Quiescent current ISHTD IVSMST IDQS 7.4 DRV Regulator The E910.27 contains a high side hysteretic regulator (CDRV) that controls its output to a voltage of VDRV below the positive high side driver input voltage VSP. This regulator limits the internal P-channel MOS transistor gate swing, provides high gate charge / discharge currents, high switching frequency and allowing high input voltage operation without exceeding the internal P-channel MOS transistor gate source breakdown voltage. If VDRV drops due any case to its lookout voltage VDRVL the ERR output will be set and internal Pchannel MOS transistor is switched off. Bypass CDRV always with a good quality temperature stable ceramic capacitor between VSP and CDRV, otherwise the chip may be damaged. To avoid substrate currents in case of very high temperatures and a fast falling edge of the input voltage a Schottky diode between CDRV and PGND may be necessary. 7.5 Error Output Pin ERR indicates fault conditions of the E910.27. These conditions are: * * * Under voltage lockout (VSM < VCRH) Driver voltage low (VDRV < VDRVL) Chip over temperature (Tj > KTMPS) ELMOS Semiconductor AG Specification 17 / 50 03SP0357E.00 05.09.2006 - Preliminary * E910.27A SMON input pin low One or more errors switch the ERR output into high impedance. If the ERR pin is not used, it should be connected to ground. The open drain output can be wired with other signals. 7.6 Reference Multiplexer A high flexibel feature of the E910.27 is its internal reference multiplexer. Due to the externally selectable MUX the user can choose between two internal precise temperature compensated or an user provided external reference. Via an external reference voltage at pin RFEX the output voltage or output current of the SMPS circuit can be controlled (e.g. for LED dimming applications or synchronous output voltage ramp up). Keep in mind that in case of disabling VSM (ENPS=false) the ESD input structures of pins RFEX, RSEL, and RLEV will clamp to ground. Input signals in this mode leads to malfunction of the E910.27 and are therefore not allowed. In any case floating of the three pins must be avoided. A save way to supply the logic levels for the multiplexer is for logically false" connect to ground and for logically true" connect to VSM. Use hard wired coding on the pc-board, because changing the mode during operating is not allowed. VCMP connected to VR1 (internal) VR2 (internal) VREXT (external) RFEX Ex. Ref Input RLEV 0 1 0 RSEL 0 0 1 7.7 Power Good, Reset Generation and Watchdog Circuitry 7.7.1 PWRGOOD Block Depending on external wiring the PWRGOOD circuit can provide POWER-GOOD, RESET or WATCHDOG behaviour. The PWGD pin open drain output can be wired OR" to other E910.27. If the PWGD pin is not used it should be connected to GND. If the external reference input (RFEX) is selected via the MUX (RSEL=true), the whole PWRGOOD block is automaticly disabled and the PWGD output stays low. For correct behaviour of the PWGD pin, there must be a minimum input voltage at VSA of 4V. 7.7.2 Power Good and Reset Timing If the switcher feedback voltage VFB decreases 15% out of nominal regulation value, the external capacitor CDLY at pin CDLY will be discharged fast by the reset generator and pin PWGD is set low. If feedback voltage VFB rises above the reset threshold, VREF-10%, CDLY will be charged with a constant current IWDC. After the power on reset time TRST the voltage on capacitor CDLY reaches VRUD and the PWGD output will be set high (high impedance) again. The value of the power on reset time TRST can be set within a wide range depending on the capacitance value of CDLY. The delay time of power on reset is defined by the charging time of the external capacitor CDLY and can be calculated as follows: TRST = (VRUD - VRLD ) CDLY IWDC [1] For power good behaviour of the circuit only, e.g. in case of ramp up sequencing of multiple power supplies, the delay capacitor CDLY is omitted. PWGD output than will react instantaneously (within TPWGD). ELMOS Semiconductor AG Specification 18 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A VS 4.5V 4.0V ENPS VSM t SMON t VOUT t VPWGDT VPWGDY VPWGD (CDLY=0nF) t Output Undefined VPWGD (CDLY=100nF) TRST TRST TRST t Output Undefined t Voltage Drop at Input Undervoltage at Output Output Voltage o.k. Overload at Output Figure 7.7.2-1: Time Response Power Good and Reset Generation ELMOS Semiconductor AG Specification 19 / 50 03SP0357E.00 05.09.2006 Shutdown - Preliminary 7.7.3 Watchdog Timing E910.27A When the voltage on the delay capacitor CDLY has reached VWUD and pin WEN was set high, the watchdog circuit is enabled and discharges CDLY with a constant current IWDD. If there is no rising edge detected at the watchdog input, CDLY will be discharge down to VWLD, then PWGD output will be set low and CDLY will be charged again with the current IWDC until VCDLY reaches VWUD and pin PWGD will be set high (high impedance) again. If a watchdog pulse, rising edge at watchdog input WDI, occurs during the discharge period, CDLY is charged again and the PWGD output stays high. After VCDLY has reached VWUD, the periodical behaviour starts once more. The watchdog timing is defined by the charging and discharging time of the external capacitor CDLY and can be calculated as follows: TWDTR = (VWUD - VWLD ) CDLY IWDD TWDP = TWDL = (VWUD - VWLD ) (IWDC + IWDD ) CDLY IWDC IWDD CDLY [2] (VWUD - VWLD ) IWDC VOUT VWDI t VCDLY TWDTR TWDP t VWUD VWLD TWDL t VPWGD t Figure 7.7.3-1: Watchdog Behaviour, Time Response Use hard wired coding of WDE on the pc-board, because changing the mode during operating is not allowed. ELMOS Semiconductor AG Specification 20 / 50 03SP0357E.00 05.09.2006 - Preliminary 7.8 Description of the SMPS Section E910.27A The E910.27 is a high input-voltage step down (buck) DC-DC converter including an internal robust P-channel MOS transistor with a typical resistance of 0.50 Ohm. This low on resistance and the possibility of 100% duty cycle assures high efficiency and a minimal dropout even at high output current level and a wide input voltage variation. By means of an on board shunt resistor current in fault conditions is limited. Together with the internal temperature supervisor the device is protected against accidental output short circuit, to avoids dangerous load damage. If the chip temperature rises higher than a fixed internal threshold (150C with 40 C hysteresis), the power stage is turned off. The E910.27 automatically switches from PWM operation at medium and heavy loads to pulse skipping operation at light loads to improve light-load efficiency without an increase in output ripple. The small size, high switching frequency, integrated P-channel MOS transistor, and the low parts count minimise the required circuit board area and component costs. The hysteretic control architecture provides for simple design without any control loop stability concerns using a wide variety of external components. The SMPS part will be switched on by a high level at Pin SMON. Due to the very wide input voltage range from 0V to VSMAX, and its CMOS compatible thresholds the SMON input can be driven by micro-controllers, bus transceivers (e.g. CAN), K15D applications and can be used for power up sequencing . ILCK CONTINUOUS MODE ICLIM IPEAK IL IOUT = IDC ITROUGH IL = IRIPPLE T1 ILCK T2 T3 t ICLIM DISCONTINUOUS MODE (CRITICAL BOUNDARY) IPEAK IL IOUT = IDC t TON TOFF Figure 7.8-1: Choke Current Waveform ELMOS Semiconductor AG Specification 21 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A 7.8.1 Operating Modes Hysteretic control does not require an internal oscillator. Switching frequency depends on external components and operating modes. Operating frequency reduces at light loads resulting in excellent efficiency compared to other architectures. When delivering low output currents, the E910.27 operates in discontinuous conduction mode (DCM). In case of delivering medium to high output currents, the E910.27 operates in PWM continuous conducted mode (CCM). In this mode, current always flows through the choke and never ramps to zero. The pulse frequency modulator (PFM) adjusts the internal P-channel MOS transistor duty cycle to maintain regulation without exceeding the peak switching current set by the external current sense resistor (RS). 7.8.2 100% Duty Cycle and Dropout The E910.27 operates with a duty cycle up to 100%. This feature extends the input voltage range by turning the internal P-channel MOS transistor on continuously when the supply voltage (VS) approaches the output voltage. This services the load when conventional switching regulators with less than 100% duty cycle would fail. Dropout voltage is defined as the difference between the input (VINPUT) and output (VOUTPUT) voltages when the input is low enough for the output to drop out of regulation. Dropout voltage depends on the internal P-channel MOS drain to source on resistance, current sense resistor (RS), and choke (LCK) series resistance and is proportional to the load current: VDROP = I OUT (RRDSON + RRS + RLCK ) [3] 7.8.3 Discontinuous Conduction Mode The E910.27 operates in discontinuous conduction mode (DCM) at light load current. In discontinuous conduction mode, current through the choke (LCK) starts at zero and ramps up to the peak as high as the voltage comparator (VCMP) limit , then ramps down to zero. Next cycle starts when the VFB voltage reaches the reference voltage. Until then, the choke current remains zero. Switching frequency is lower and switching losses reduce. The switching frequency depends on input voltage, output capacitor and output load. The switch waveform (Pin SWD) can exhibit ringing, which occurs at resonant frequency of the choke and stray capacitance, due to residual energy stored in the core when the commutation diode (DSW) turns off. 7.8.4 Continuous Mode PFM Control Behaviour The E910.27 PFM controller has an unique regulation scheme that allows PWM operation at medium and high output current with automatic switching to pulse skipping mode at lower currents to improve light load efficiency. Under medium and heavy load operation, the choke (LCK) current is continuos and the SMPS part operates in PWM mode. Current always flows through the choke and never ramps down to zero. In this condition, the switching frequency is set by either the minimum on-time (TONM), or the minimum off-time (TOFFM), depending on the duty cycle. The duty cycle is: Duty VINPUT VOUTPUT + Vd DSW + IOUT MAX RDC CHOKE + Vd DSW - IOUT MAX (RS + RDS ON + RDC CHOKE ) [4] If the duty cycle is less than 33%, the minimum on-time (TONM) controls the switching frequency. The operating frequency is approximately: ELMOS Semiconductor AG Specification 22 / 50 03SP0357E.00 05.09.2006 - Preliminary Fop Duty 1000 kHz Duty TONM E910.27A [5] If the duty cycle is greater than 33%, the off-time (TOFFM) sets the switching frequency. The operating frequency is approximately: Fop (1 - Duty ) 500kHz (1 - Duty ) TOFFM [6] In both cases the voltage is regulated by the voltage comparator (VCMP). For low duty cycles (<33%) the internal P-channel MOS transistor is turned on for the minimum on-time (TONM), causing fixed on-time operation. During the internal P-channel MOS transistor's on-time the output voltage rises. Once the internal Pchannel MOS transistor is turned off, the voltage drops to the regulation threshold set by the external voltage divider (RFB1 and RFB2), and another cycle is initiated. For high duty cycles (>33%) the internal P-channel MOS transistor remains off for the minimum off-time (TOFFM) causing fixed off-time operation. In this case the internal P-channel MOS transistor remains on, until the output voltage rises to the regulation threshold set by the external voltage divider (RFB1 and RFB2). Then the internal P-channel MOS transistor turns off for the minimum off-time (TOFFM) and the next cycle starts. Duty > 33%, TOFF = const = TOFFM Duty < 33%, TON = const = TONM FREQUENCY VINPUT Figure 7.8.4-1: Relative Switching Frequency in Continuous Conduction Mode An unique regulation feature of the PFM controller is its automaticly selection of fixed on-time or fixed off-ime mode. By switching between fixed on-time and fixed off-time operation the E910.27 can operate at high input to output ratios, yet still operate up to 100% duty cycle for low dropout. When transitioning from fixed on-time to fixed off-time mode, the output voltage drops slightly due to the output ripple voltage. In fixed on-time operation the minimum output voltage is regulated, while in fixed off-time operation the maximum output voltage is regulated. Thus, as the input voltage drops below approximately three times of the output voltage, a decrease in line regulation can be expected. The output voltage drop is about: ELMOS Semiconductor AG Specification 23 / 50 03SP0357E.00 05.09.2006 - Preliminary VRIPPLE 2 E910.27A VDROP _ OP [7] At light output loads, the choke current is discontinuous, takes the E910.27 to switch at lower frequencies and decreasing the internal P-channel MOS transistor's gate drive and switching losses. Under most circumstances in discontinuous mode the on-time will be fixed to the minimum on-time of TONM. If the choke (LCK) inductance value is small or the current sense resistor (RS) is large the current limit will be reached before the minimum on-time (TONM), terminating the on-time and overwrite it. If the impedance of the feedback divider is too high, or the choke (LCK) inductance is too large, or the output capacitance (COUT) is too high and equivalent series resistance (ESR) is too low, then the internal P-channel MOS transistor remains on longer than the minimum on-time (TONM) until the output capacitor charges beyond the voltage comparators (VCMP) hysteresis of about VHYST and causing the controller to operate in hysteretic mode. Operating in hysteretic mode results in lower switching frequency operation. RFB1 VHYST 4mV 1 + RFB 2 [8] The E910.27 requires a certain ESR value for proper operation. The transition to hysteretic mode occurs at the critical output capacitor ESR: C _ ESRCRITICAL VHYST I RIPPLE [9] In the above equation IRIPPLE is the choke ripple current and can be approached, for duty cycle less than 33%, by: I RIPPLE (VINPUT - VOUTPUT - IOUT MAX ( RS + RDS ON ) ) TONM LCK [10] Where TONM is the minimum on-time for minimum on-time control, or in case of duty cycle greater than 33%: I RIPPLE (VOUTPUT + Vd DSW ) TOFFM LCK [11] Where TOFFM is the minimum off-time for minimum off-time mode. 7.8.5 Leading Edge Blanking A leading edge blanking timer (TBLK) avoids an erratic operation through spikes at RSIN input while switching on the internal P-channel MOS transistor. The same timer suppresses also a quasi-analogue operation of the internal P-channel MOS transistor by means of too small gate drive pulses. Too small gate pulses lead to internal overheating and the complete SMPS is switched off. ELMOS Semiconductor AG Specification 24 / 50 03SP0357E.00 05.09.2006 - Preliminary 7.8.6 Run Away at Start-up and Output Short E910.27A Under start-up or output short condition, the PFM will switch the internal P-channel MOS transistor always on to bring the output voltage in tolerance. When the voltage across RS caused by the high switch current reaches the threshold level (VCLIM) of the comparator CCMP, it resets the PFM and therefore the internal P-channel MOS transistor is immediately switched off. After the fixed off-time (TOFFM) the internal P-channel MOS transistor starts to conduct again. The required duty cycle in this short circuit situation is: Duty Short VINPUT Vd DSW + VRLCK - Von PMOS - VRS + Vd DSW [12] Depending on input voltage VS (especially at high input voltages), inductance values for the choke, internal P-channel MOS transistors on resistance and impedance of the rest of external components it is not always possible to keep the duty to the required small value. When this happens the current through the circuit is rising from period to period, until the output voltage reaches a value for the duty cycle that the E910.27 can handle, or reaches a maximum current, limited by the cumulated resistances in the buck path only. In this inrush current situation, the external components may be over stressed and / or the internal thermo protection switches off the whole SMPS. Normally this start-up time period is very short and the effect takes no matter. To handle this current run away, the user can select with pin SDLY=true, a longer off-time option (TOFFMS), that takes place the minimum off-time (TOFFM) in case of triggering the current comparator CCMP only. Due to the reduced stored energy per switching cycle, ramp up duration of the whole supply takes somewhat longer. However, be careful there may be combinations of external component values (especially too low or too high inductance values for the choke), which prevents successful start-up of the supply. ELMOS Semiconductor AG Specification 25 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A 8 Design Information 8.1 Design Guidelines External component selection is driven by output to input voltage ratio (duty cycle), ripple current and maximum output load. The circuit design is an iterative process and must be carefully proved by testing of your prototype. First calculate the appropriate duty cycle range for your circuit, then proceed as follows. 8.1.1 Output Voltage Setting The step down converters output voltage is set using the following equation, where RFB2 is connected between the VFB pin and SGND, and RFB1 is connected between VOUTPUT and the VFB pin. V RFB1 = OUTPUT - 1 RFB 2 VREF [13] Where VREF is 200mV, 1.2V or externally by user provided in the range of 0V to 1.3V. Output voltage ripple causes the output voltage to be higher or lower than set by the resistor divider at the feedback pin VFB. If the application runs with minimum on-time, the ripple (half of the peak to peak value) adds to the output voltage. In the case of working with minimum off-time, the output voltage is lower by the amount of ripple (half of the peak to peak value) at the output. The input bias current at VFB loads the divider, therefore RFB2 should not be set too high-valued resistor to obtain high accuracy. A divider current of 120A or higher is recommend. The feedback voltage line can be sensitive to noise. Avoid inductive coupling to the choke or the switching node, by keeping the VFB trace away from these areas. In some applications, depending on board layout, the capacitance may be too high from pin VFB to GND. In this case, the internal comparator may not switch fast enough to operate with the minimum on-time or the minimum off-time given in this data sheet. For such applications a small feedforward capacitor (CFF) should be added in parallel with RFB1 to speed up the internal voltage comparator. On the other hand in some applications, depending on board layout, a small capacitor (some pF) in parallel to RFB2 might be necessary for stable operation. But this changes the operating frequency range too. 8.1.2 Current Sense Resistor Selection In case of SMPS ramping up, heavy output load, or shorted output, the current sense comparator CCMP limits the peak switching current to VCLIM/RS, where RS is the value of the current sense resistor and VCLIM is the current sense threshold. Minimising the peak switching current will increase efficiency and reduce the size and cost of external components. But, since available output current is a function of the peak switching current the peak limit must not be set too low. A good value is setting the peak current limit to 1.20 times the maximum load current by calculating the current sense resistor to: . RS VCLIM MIN I 1.20 IOUT MAX + RIPPLE 2 [14] This takes the normal coke's inductance value tolerance into account. The maximum RMS current in continuous operating mode is (take "r" from the calculations below): ELMOS Semiconductor AG Specification 26 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A IRS RMS = IOUT MAX DMAX r2 1 + 12 [15] For 100% duty cycle we get: IRS RMS = IOUT MAX [16] The current sense resistor's power rating should be: P _ RS = VCLIM MAX RS 2 [17] 8.1.3 Choosing the Choke Value The E910.27 operates with a wide range of inductance values. The inductance mainly determines the choke current ripple. Lower values are chosen to reduce physical size of the choke. Higher values allow more output current because they reduce peak current seen by the internal P-channel MOS transistor. Higher values also reduce output ripple voltage, and core loss. When choosing a choke you might have to consider maximum load current, core and copper losses, allowable component height, output voltage ripple, EMI, fault current in the choke, saturation, and of course, cost. Since the choke value determines the output ripple current, you have to decide the ratio of the ripple current to the output current. The ripple current is depending on the duty cycle. Take the worst case ripple current value of your application. r= I L I = RIPPLE IOUTMAX IOUTMAX [18] The core-material losses (magnetic hysteresis loss, eddy-current loss), skin-effect and proximity-effect losses in the conductor and radiation losses increases substantially with increasing "r". Calculations show, the most optimum choice happens when this ratio "r" is set between 0.2 and 0.4 at the maximum output current. Often r=0.3 is used. Note that this is just a guideline for an economic design. I RIPPLE 0.3 IOUT MAX [19] If the converter should work in continous mode, even with the lowest output current, than the ripple ratio must yet be lower: I RIPPLE 2 IOUT MIN [20] The first step in choke design is to determine the appropriate operating mode of the E910.27. Calculate the minimum inductance value of the choke in continuous mode as follows. ELMOS Semiconductor AG Specification 27 / 50 03SP0357E.00 05.09.2006 - Preliminary Equation A: E910.27A LCK (VOUTPUT + Vd DSW + IOUTMAX RDC CHOKE ) TOFFM I RIPPLE [21] Equation B: LCK (VINPUT - VOUTPUT - IOUT MAX ( RS + RDS ON + RDC CHOKE ) TONM I RIPPLE [22] With RDCCHOKE = choke resistance and RDSON = P-channel MOS transistor "ON" resistance. Case A, minimum input voltage Determine the duty cycle for minimum input voltage VS. If the duty cycle is greater than 33% take equation A. If the duty cycle is lower than 33% take equation B. Case B, maximum input voltage Determine the duty cycle for maximum input votage VS. If the duty cycle is greater than 33% take equation A. If the duty cycle is lower than 33% take equation B. Compare the calculation results from case A and case B and take the highest inductance value. Use the next greater standard inductance value. For optimum efficiency, the choke winding's resistance should be not larger than the current sense resistance (RS). Calculate peak choke current at worst case to ensure that the choke will not saturate over temperature. Ferrite cores saturate abruptly. Peak current can be significantly higher than output current. IChoke SAT 1.25 VCLIM MAX RS MIN [23] Decide if your circuit can tolerate an magnetic open core geometry like a rod or barrel (drum), which have high magnetic field radiation, or whether it needs a closed core like an U-, E- or toroid to prevent EMI problems. 8.1.4 Choosing the Input and the Output Capacitor Choose the input capacitor CIN and the output capacitor COUT to manage the input and output peak currents with acceptable voltage ripple. The value of the output capacitor depends on the output voltage ripple requirements as well as the maximum voltage deviation during load transients. ESR of the output capacitor and the value of the choke are the major source of output voltage ripple, so low ESR capacitors are recommended. Keep in mind that specifically standard aluminium electrolytic capacitors have a large ESR variation over temperature and lifetime. For good EMI behaviour, the ESL of the output capacitor should also be low. Output voltage ripple is the sum of contributions from ESL, ESR and capacitance value: VOUT RIPPLE = VRIPPLE ESL + VRIPPLE ESR + VRIPPLE CVAL [24] The output voltage ripple in continuous mode due to the ESR is approximately: VRIPPLE ESR RESR I RIPPLE [25] ELMOS Semiconductor AG Specification 28 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A The output capacitance typically increases with load transient requirements. During the time between the load transient and turn-on of the internal P-channel MOS transistor, the output capacitor must supply all the current required by the load. This current supplied by the output capacitor results in a voltage drop across the ESR that is substracted from the output voltage. For a load step from near zero output current (discontinuous conduction mode) to its maximum (continuous conduction mode), the following equation can be used to calculate the required output capacitance. I LCK IOUT MAX + RIPPLE VINPUT 2 COUT V 2 VOUTPUT VRIPPLE CVAL INPUT - VOUTPUT 2 [26] If the worst case load step is not so extremely large and the E910.27 stays always in continuous conduction mode, a much smaller capacitance value for COUT is possible. 2 LCK I L V INPUT COUT V VOUTPUT VRIPPLE CVAL INPUT - VOUTPUT [27] Where IL is the change in choke current, therefore minimum IRIPPLE. Obtain an output ripple voltage lower than the system hysteresis (VHYST) is not practical, since the E910.27 will switch at slower frequencies and increases choke ripple current. The output capacitor COUT also needs therefore to be at least big enough to handle the worst case RMS current through it. ICOUTRMS = IOUTMAX r 12 [28] Estimate the input capacitor capacitance value for a given maximum voltage ripple in continuous mode as follows: I LCK IOUT MAX + RIPPLE 2 CIN 2 V INPUT VRIPPLE CIN 2 [29] In a buck converter the input capacitor CIN must carry a high RMS current because of the currents pulsating nature. The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple at VINPUT. Use a low ESR capacitor type. For good EMI behaviour, the ESL of the input capacitor should be also very low. Two or more smaller value low ESR capacitors connected in parallel work often better than a single larger one. Place ceramic capacitors very close from VSA and VSP to GND. In continuous conduction mode, the input capacitor must be able to handle the whole RMS current of the converter with the worst case duty cycle of your application. r2 ICIN RMS = IOUTMAX Duty 1 - Duty + 12 [30] ELMOS Semiconductor AG Specification 29 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A These equations are suitable for initial capacitor selection. Final values should be set by testing of your prototype circuit. 8.1.5 Catch Diode Selection The catch diode DSW carries load current during the internal P-channel MOS transistors off-time. Therefore the average diode current is depending on the duty cycle. At high input to output voltage ratios the diode conducts most of the time. The most stressful condition for the diode is when the output is shorted. Under this condition the diode must safely handle a peak current of: IDSW PEAK 2 VCLIM MAX RS MIN [31] The catch diode maximum forward loss in continuous conduction mode is: PDSW MAX IDSW AVG Vd DSW [32] Where VdDSW is the maximum forward drop from the diode data sheet and IDSWAVG is the average current at the minimum duty cycle: IDSW AVG = IOUTMAX (1 - Duty ) [33] The reverse (blocking) voltage VRRM of the catch diode must be at minimum VINPUTMAX . The E910.27 high switching frequency requires a high speed rectifier DSW. The catch diode is the biggest EMI source in the circuit. Take therefore care of diode selection. Surface mount low reverse leakage Schottky diodes are recommended for low output voltages. Ultra high speed soft recovery rectifiers with reverse recovery times < 30ns should be used for moderate or high output voltages, where the increased forward drop causes less efficiency degradation. 8.1.6 Snubber Network Design For low output current, in discontinuous conduction mode, the internal P-channel MOS transistor turns off, and the energy stored in the inductance would cause oscillations with the parasitic capacitances without a snubber network. Typically there are little losses in parasitic resonant circuits so many cycles of ringing normally occur. This oscillation may be an EMI issue. If required an RC snubber will easily damp the ringing. If the snubber resistance is equal to the characteristic impedance of the resonant circuit then the resonant circuit will be critically damped. Once the circuit has been build and is operating, the values of the snubber components may be evaluated experimentally. Start with a small value of capacitor CSN and place it in the circuit directly across the catch diode DSW, and observe the voltage waveform with and without the capacitor in the circuit. Increase the value of the capacitor until the frequency of the ringing to be damped has been halved. This is a near optimum value for the capacitor CSN since it allows damping very near Q=1. Add a resistor in series with the snubber capacitor and choose its value for optimum, so that the ringing will be aperiodic damped. RSN 2 fres LCK [34] Where fres = initially measured resonant frequency, and LCK = choke inductance. ELMOS Semiconductor AG Specification 30 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A The amount of power dissipation is independent of the value of the resistor RSN. If the time constant of the snubber network is short compared to the switching period of the converter but is long compared to the voltage rise time, than the loss can be estimated by: P _ RSN Fop CSN VINPUT 2 [35] With Fop = switching frequency of the converter and VINPUT = maximum input voltage. without snubber aperiodic damped Figure 8.1.6-1: Discontinuous Mode Switch Drain Voltage without and with Snubber 8.1.7 Maximum available Output Current versus Internal Losses and Operating Temperature The internal E910.27 DC-DC converter losses are a combination of quiescent device power, dynamic gate driver power and P-channel MOS transistors switching losses. In any case the maximum allowed peak drain current of the internal P-channel MOS transistor must not exceed ISWD. With the maximum continuous output current of the buck converter and the specified maximum operating temperature, the chip temperature must be well lower than the thermal shutdown limit. The maximum available output current of the converter depends on maximum duty cycle, switching frequency (dynamic losses) and the thermal transfer of the package provided by the external heat sinking (e.g. printed circuit board). ELMOS Semiconductor AG Specification 31 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A The crossover losses are lowest at minimum input voltage. But they are usually a small fraction of the conduction losses, they can be sometimes ignored. For 100% duty cycle we get the worst case RMS current through the internal P-channel MOS transistor.The maximum RMS current through the switch in continuous conduction mode over duty cycle can be calculated by: r2 IPMOS RMS = IOUTMAX Duty 1 + 12 [36] The effective ON-resistance of the E910.27 over junction temperature can be approximated by: RDSON ( 470m + 1.41m TJ + 2.85 TJ ) [37] In continuous conduction mode the total device power loss can be approximated using the following equation: 2 PDEVTOT VINPUT IDQS + IPMOS RMS RDSON + VINPUT Fop (0.5 IOUTMAX (tON + tOFF ) + QDS ) 2 [38] Where: tON = P-channel MOS transistor turn on time tOFF = P-channel MOS transistor turn off time QDS = P-channel MOS transistor gate driver charge Typically values for the E910.27 are: tON ~ 20ns tOFF ~ 30ns QDS ~ 10nQ When maximum junction temperature and maximum operating temperature are known, their difference indicates the permissible junction temperature rise for the given application. The thermal resistance path must ensure that the product PDEV x RTAJ is lower than this difference. The maximum possible device power loss can by calculated by: PDEV MAX Where: TAMAX = maximum operating temperature TJ MAX -TAMAX RTAJ [39] TJMAX = maximum save junction temperature, about 135C RTAJ = thermal resistance junction to ambient. ELMOS Semiconductor AG Specification 32 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A 50 Thermal Resistance Junction to Ambient [C/W] 45 TSSOP24 ADT-1 Package 70m Cu, Copper Clad PC-Board 40 35 30 25 5 10 15 20 25 30 35 40 45 50 55 Heat Sink Area [cm] Figure 8.1.7-1: Typical Thermal Resistance (RTAJ) versus PC-Board Area Always use a ground plane under the step-down converter to minimise interplane coupling and provide the required heat sinking. The typically thermal resistance for a given PC-board area can be read in the above diagram. By further reducing of the thermal resistance due to an additional external heat sinking (e.g. case) a maximum power loss of about 1.6W is possible. ELMOS Semiconductor AG Specification 33 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A 9 PCB Layout Considerations The PC board layout is very important in all high-frequency switching converter designs. Poor layout can cause switching noise into the feedback signal and may degrade performance and is general the source of heavy EMI problems. VIN C3 R1 C4 C5 RSIN1 SMON RSIN2 ENPS VSA VSP CDRV Connect exposed pad to analog ground ERR PWGD WDI WDE CDLY VSM AGND PGND E910.27 D1 C1 SWD1 SWD2 L1 VOUT SGND RFEX RLEV C2 SDLY RSEL GND VFB Keep feedback wiring away from choke flux Separate analog ground from power ground Keep very short R3 R2 Figure 9-1: Typical Converter Schematic for PCB Layout For minimal inductance, the wires indicated by heavy lines should be as wide and short as possible. Keep the ground pin of the input capacitor (C5) as close as possible to the anode of the catch diode (D1), snubber network (if there is any) and output capacitor (C1). This path carries a large AC current. The switching node, the node with the catch diode cathode, choke, and internal P-channel MOS transistor drain (SWD1 & SWD2), should be kept short. This node is one of the main sources for radiated EMI since it is an AC voltage with switching frequency. It is always a good practice to use a ground plane in the design of the PC board, particularly at high frequency currents. The three ground pins, AGND, SGND and GND, should be connected by as short a trace as possible. The ground pins should be tied to the ground plane, or to a large ground trace in close proximity to both the VFB divider and then should be connected to PGND pin and the output capacitor (C1) grounds. The VFB pin is a high impedance node and care should be taken to make the VFB trace short to avoid noise pickup, inaccurate regulation and erratic function of the PWGD output. The feedback resistors should be placed as close as possible to the E910.27, with the ground of R3 placed as close as possible to the SGND of the E910.27. Avoid inductive coupling to the choke or the switching node, by keeping the VFB trace away from these areas. Radiated noise can be decreased by choosing a shielded version for the choke. Refer to the E910.27 demo board as an example layout. ELMOS Semiconductor AG Specification 34 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A 10 Applications Information ELMOS Semiconductor AG Specification 35 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A 10.1 Block X1 10.1.1 Block Diagram Figure 10.1.1-1: Blockdiagram of Block X1 10.1.2 Functional Description ELMOS Semiconductor AG Specification 36 / 50 03SP0357E.00 05.09.2006 - Preliminary 10.2 Application Gallery E910.27A VIN C3 R1 C4 C5 SMON VSA ENPS VSP CDRV RSIN1 ERR PWGD WDI WDE CDLY VSM AGND PGND E910.27 D1 C1 SWD1 SWD2 L1 VOUT SGND RFEX C6 C2 R2 R3 R4 SDLY RLEV RSEL GND VFB RSIN2 RESB TRIG P VOUT = 3.3V -> VIN = 4.5V to 40V VOUT = 5.0V -> VIN = 6V to 40V Figure 10.2-1: P Power Supply with RESET and Watchdog VIN C3 BAT CANL INH R1 C4 C5 SMON VSA ENPS VSP CDRV RSIN1 CANH ERR PWGD WDI CAN-TRANSCEIVER WDE CDLY VSM AGND RSIN2 SWD1 SWD2 L1 VOUT D1 C1 E910.27 PGND SGND RFEX C6 C2 R2 R3 R4 SDLY RLEV RSEL GND VFB RESB TRIG P !5A Stand-By Current Figure 10.2-2: P Power Supply Wake-Up by CAN-Transceiver ELMOS Semiconductor AG Specification 37 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A VIN C3 R1 C4 C5 SMON VSA ENPS VSP CDRV RSIN1 ERR PWGD WDI WDE CDLY VDD 5V CMOS P GND PORT C2 VSM AGND PGND E910.27 D1 C1 SWD1 SWD2 L1 VOUT SGND RFEX RLEV R2 R3 Internal Linear Regulator can deliver up to 12mA to external CMOS P Figure 10.2-3: Main Power Supply Wake-Up by auxiliary CMOS Processor D2 K30 C8 C7 L2 C3 R1 C4 C5 RSIN1 SMON K15 ERR C10 RSIN2 VSA ENPS VSP CDRV R5 SDLY RSEL GND VFB RSIN2 PWGD WDI WDE CDLY VSM AGND E910.27 SWD1 SWD2 D1 R4 L1 VOUT1 C1 C9 PGND SGND RFEX RLEV C6 C2 R2 R3 R5 SDLY RSEL GND VFB RESB TRIG VOUT2 5V P 15A Stand-By Current Figure 10.2-4: Discontinous Mode Automotive Power Supply ELMOS Semiconductor AG Specification 38 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A VIN C3 MOTON R1 C4 C5 SMON VSA ENPS VSP CDRV RSIN1 ERR PWGD WDI WDE CDLY VSM AGND PGND C6 E910.27 D1 R4 C1 SWD1 SWD2 L1 VOUT RSIN2 M SGND RFEX RSEL C2 DATA DAC R2 R3 SDLY RLEV GND VFB - 0 to 100% VOUT Range - 180A Stand-By Current Figure 10.2-5: External programmable Power Amplifier VIN C3 ON R1 C4 C5 D2 VOUT2 SMON VSA ENPS VSP CDRV RSIN1 RSIN2 C7 ERR POK PWGD WDI WDE CDLY VSM C6 AGND PGND E910.27 D1 R4 C1 SWD1 L1 SWD2 VOUT1 SGND RFEX RSEL C2 R2 R3 - VOUT2 tracks VOUT1 - POUT1 must be greater then POUT2 - For negative VOUT2 reverse D2, C7 and secondary winding of L1 Figure 10.2-6: Step-Down Converter with tracking auxiliary Output ELMOS Semiconductor AG Specification 39 / 50 SDLY RLEV GND VFB 03SP0357E.00 05.09.2006 - Preliminary - E910.27A VIN C3 LDON R1 C4 C5 SMON VSA ENPS VSP CDRV RSIN1 ERR PWGD WDI WDE CDLY VSM AGND PGND E910.27 D1 C1 SWD1 SWD2 L1 RSIN2 SGND RFEX RSEL RLEV C2 SDLY LED1 GND VFB LED2 R2 - 15A Stand-By Current - VIN = 5V to 40V with one 1A Power LED - VIN = 10V to 40V with two 1A Power LED Figure 10.2-7: Extremely low Stand-By Current high efficiency 1A LED Driver VIN C3 LDON R1 C4 C5 SMON VSA ENPS VSP CDRV RSIN1 ERR PWGD WDI WDE CDLY VSM AGND PGND C6 E910.27 D1 R3 C1 SWD1 SWD2 L1 RSIN2 SGND RFEX RSEL C2 SDLY RLEV LED1 GND VFB LED2 DIML R2 - 0 to 100% Dimming Range - 180A Stand-By Current - VIN = 5V to 40V with one 1A Power LED - VIN = 10V to 40V with two 1A Power LED Figure 10.2-8: High efficiency Step-Down 1A LED Driver with Dimming ELMOS Semiconductor AG Specification 40 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A VIN C3 LDON R1 C4 C5 VSA ENPS VSP SMON CDRV RSIN1 ERR PWGD WDI WDE CDLY VSM C6 AGND PGND E910.27 D1 R3 C1 SWD1 SWD2 L1 RSIN2 SGND RFEX RSEL C2 SDLY RLEV LED1 LED2 LEDn GND VFB R4 R5 Rn DIML R2 - 0 to 100% Dimming Range - 180A Stand-By Current - Up to 1.2A total Output Current - VIN = 5.5V to 40V Figure 10.2-9: Dimmable high current LED Cluster Driver VIN C3 LDON R1 C4 C5 SMON VSA ENPS VSP CDRV RSIN1 ERR PWGD WDI WDE CDLY VSM AGND PGND E910.27 D1 C1 SWD1 SWD2 L1 RSIN2 SGND RFEX RSEL RLEV C2 SDLY LED1 GND VFB LED2 R6 R3 T1 R4 T2 R7 R8 NTC R5 R2 - 15A Stand-By Current - VIN = 5V to 40V with one 1A Power LED - VIN = 10V to 40V with two 1A Power LED - Thermo Protection, e.g. above 85C Figure 10.2-10: 1A LED Driver with temperature Protection ELMOS Semiconductor AG Specification 41 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A VIN C3 ON R1 C4 C5 SMON VSA ENPS VSP CDRV RSIN1 ERR PWGD WDI WDE R4 CDLY VSM AGND PGND E910.27 D1 C1 SWD1 SWD2 L1 VOUT1 SGND RFEX RLEV C2 R2 R3 C9 SDLY R5 RSEL GND VFB RSIN2 C6 C7 VSA ENPS VSP SMON CDRV RSIN1 ERR PWGD WDI WDE CDLY VSM AGND PGND E910.27 D2 C10 SWD1 SWD2 L2 VOUT2 SGND RFEX C8 R6 R7 ON MASTER (VOUT1) SLAVE (VOUT2) T Figure 10.2-11: Power-Up Sequencing Example ELMOS Semiconductor AG Specification 42 / 50 SDLY RLEV RSEL GND VFB RSIN2 03SP0357E.00 05.09.2006 - Preliminary 11 Package 11.1 Marking E910.27A 11.1.1 Top Side ELMOS (Logo) E 910.27A XXX#YWW*@ where E/M/T 910.27 A XXX # YWW * @ Volume Production / Prototype / Test Circuit ELMOS Project Number Version Lot Number Assembler Code Year and Week of Fabrication Mask Revision Number ELMOS internal Marking 11.1.2 Bottom Side No Marking ELMOS Semiconductor AG Specification 43 / 50 03SP0357E.00 05.09.2006 - Preliminary 11.2 Package Dimensions E910.27A Thermally Enhanced Variation Figure 11.2-1: Package Outlines of TSSOP24 ADT-1 ELMOS Semiconductor AG Specification 44 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A ELMOS Semiconductor AG Specification 45 / 50 03SP0357E.00 05.09.2006 - Preliminary 12 General 12.1 ELMOS Documents QM-Nr.: 07PL0009.XX Standard Qualifikations Plan QM-Nr.: 07SP0001.XX Reliability Test Methods QM-Nr.: 07VA0013.XX Reliability Testing QM-Nr.: 07VA0005.XX Finalpart Release for Shipment QM-Nr.: 07SP0028.XX Taping of Devices E910.27A ELMOS Semiconductor AG Specification 46 / 50 03SP0357E.00 05.09.2006 - Preliminary 13 Record of Revisions Chapter Rev. Change and Reason for Change 1 Initial Revision 2 Complete Rework Date 17.11.05 E910.27A Released FJP FJP ELMOS Semiconductor AG Specification 47 / 50 03SP0357E.00 05.09.2006 - Preliminary 14 Index E910.27A Table of Content 1 General...........................................................................................................................................................2 1.1 WARNING - Life Support Applications Policy.......................................................................................2 1.2 General Disclaimer................................................................................................................................2 1.3 Application Disclaimer............................................................................................................................2 1.4 Contact...................................................................................................................................................2 2 Pinout.............................................................................................................................................................3 2.1 Pin Description.......................................................................................................................................3 2.2 Package Pinout......................................................................................................................................5 3 Basic Blockdiagram........................................................................................................................................6 4 Operating Conditions.....................................................................................................................................7 4.1 Absolute Maximum Ratings...................................................................................................................7 4.2 Recommended Operating Conditions...................................................................................................9 5 Detailed Electrical Characteristics...............................................................................................................10 5.1 Supply Voltage and Currents...............................................................................................................10 5.2 Low Drop Internal Voltage Regulator...................................................................................................10 5.3 Internal VSM Undervoltage Lockout Level..........................................................................................10 5.4 MUX.....................................................................................................................................................11 5.5 Voltage Comparator.............................................................................................................................11 5.6 Current Comparator.............................................................................................................................11 5.7 Pulse Frequency Modulator.................................................................................................................12 5.8 Power Stage.........................................................................................................................................12 5.9 Error Output and Optional Short Detection Delay Input......................................................................12 5.10 Power Good / Reset and Watchdog Stage........................................................................................12 5.11 Thermal Shutdown.............................................................................................................................13 6 Typical Performance Characteristics...........................................................................................................14 7 Functional Description..................................................................................................................................16 7.1 Operation.............................................................................................................................................16 7.1.1 Typical Application Circuit............................................................................................................16 7.1.2 Introduction..................................................................................................................................16 7.2 Linear Regulators.................................................................................................................................17 7.2.1 Internal Power Supply..................................................................................................................17 7.2.2 VSM Regulator.............................................................................................................................17 7.3 Device Quiscent Currents....................................................................................................................17 7.4 DRV Regulator.....................................................................................................................................17 7.5 Error Output.........................................................................................................................................17 7.6 Reference Multiplexer..........................................................................................................................18 7.7 Power Good, Reset Generation and Watchdog Circuitry....................................................................18 7.7.1 PWRGOOD Block........................................................................................................................18 7.7.2 Power Good and Reset Timing...................................................................................................18 7.7.3 Watchdog Timing.........................................................................................................................20 7.8 Description of the SMPS Section.........................................................................................................21 7.8.1 Operating Modes.........................................................................................................................22 7.8.2 100% Duty Cycle and Dropout....................................................................................................22 7.8.3 Discontinuous Conduction Mode.................................................................................................22 ELMOS Semiconductor AG Specification 48 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A 7.8.4 Continuous Mode PFM Control Behaviour..................................................................................22 7.8.5 Leading Edge Blanking................................................................................................................24 7.8.6 Run Away at Start-up and Output Short......................................................................................25 8 Design Information.......................................................................................................................................26 8.1 Design Guidelines................................................................................................................................26 8.1.1 Output Voltage Setting.................................................................................................................26 8.1.2 Current Sense Resistor Selection...............................................................................................26 8.1.3 Choosing the Choke Value..........................................................................................................27 8.1.4 Choosing the Input and the Output Capacitor.............................................................................28 8.1.5 Catch Diode Selection.................................................................................................................30 8.1.6 Snubber Network Design ............................................................................................................30 8.1.7 Maximum available Output Current versus Internal Losses and Operating Temperature .........31 9 PCB Layout Considerations.........................................................................................................................34 10 Applications Information ............................................................................................................................35 10.1 Block X1.............................................................................................................................................36 10.1.1 Block Diagram............................................................................................................................36 10.1.2 Functional Description...............................................................................................................36 10.2 Application Gallery.............................................................................................................................37 11 Package.....................................................................................................................................................43 11.1 Marking..............................................................................................................................................43 11.1.1 Top Side.....................................................................................................................................43 11.1.2 Bottom Side...............................................................................................................................43 11.2 Package Dimensions.........................................................................................................................44 12 General.......................................................................................................................................................46 12.1 ELMOS Documents...........................................................................................................................46 13 Record of Revisions...................................................................................................................................47 14 Index...........................................................................................................................................................48 ELMOS Semiconductor AG Specification 49 / 50 03SP0357E.00 05.09.2006 - Preliminary - E910.27A Table of Figures Figure 2.2-1: Pinout TSSOP24 ADT-1................................................................................................................5 Figure 3-1: Blockdiagram....................................................................................................................................6 Figure 7.1.1-1: Typical Application Circuit........................................................................................................16 Figure 7.7.2-1: Time Response Power Good and Reset Generation..............................................................19 Figure 7.7.3-1: Watchdog Behaviour, Time Response.....................................................................................20 Figure 7.8-1: Choke Current Waveform............................................................................................................21 Figure 7.8.4-1: Relative Switching Frequency in Continuous Conduction Mode.............................................23 Figure 8.1.6-1: Discontinuous Mode Switch Drain Voltage without and with Snubber....................................31 Figure 8.1.7-1: Typical Thermal Resistance (RTAJ) versus PC-Board Area...................................................33 Figure 9-1: Typical Converter Schematic for PCB Layout................................................................................34 Figure 10.1.1-1: Blockdiagram of Block X1......................................................................................................36 Figure 10.2-1: P Power Supply with RESET and Watchdog..........................................................................37 Figure 10.2-2: P Power Supply Wake-Up by CAN-Transceiver.....................................................................37 Figure 10.2-3: Main Power Supply Wake-Up by auxiliary CMOS Processor...................................................38 Figure 10.2-4: Discontinous Mode Automotive Power Supply.........................................................................38 Figure 10.2-5: External programmable Power Amplifier...................................................................................39 Figure 10.2-6: Step-Down Converter with tracking auxiliary Output................................................................39 Figure 10.2-7: Extremely low Stand-By Current high efficiency 1A LED Driver...............................................40 Figure 10.2-8: High efficiency Step-Down 1A LED Driver with Dimming.........................................................40 Figure 10.2-9: Dimmable high current LED Cluster Driver...............................................................................41 Figure 10.2-10: 1A LED Driver with temperature Protection............................................................................41 Figure 10.2-11: Power-Up Sequencing Example.............................................................................................42 Figure 11.2-1: Package Outlines of TSSOP24 ADT-1.....................................................................................44 ELMOS Semiconductor AG Specification 50 / 50 03SP0357E.00 05.09.2006 |
Price & Availability of E91027A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |